1. Field of the Invention
This invention relates generally to semiconductor circuitry and, more particularly, to three dimensional vertical semiconductor devices.
2. Description of the Related Art
Advances in semiconductor manufacturing and digital systems architecture have provided chips or integrated circuits with many millions of active and passive circuit components, along with the interconnects needed to create the desired circuit networks. Active devices typically include transistors and passive devices typically include resistors, capacitors, and inductors. As is well-known, most integrated circuits include transistors that are primarily implemented on a single major surface of a substrate, such as a semiconductor wafer. These laterally oriented devices consume significant amounts of chip area. Over a number of years, manufacturing advances related to transistors and interconnects have primarily been directed to reducing the lateral dimensions thereof so that more devices per unit area can be placed on a chip. However, the equipment and technologies required to fabricate such highly integrated chips becomes increasingly expensive with each new generation of smaller devices. Accordingly, what is needed are structures and methods that are suitable for providing increased circuit density in integrated circuits without necessarily requiring devices to be made smaller.